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1 for more information www.linear.com/3375 typical a pplica t ion fea t ures descrip t ion 8-channel programmable, parallelable 1a buck dc/dcs the lt c ? 3375 is a digitally programmable high efficiency multioutput power supply ic. the dc/dcs consist of eight synchronous buck converters (i out up to 1a each) all powered from independent 2.25v to 5.5v input supplies. dc/dc enables, output voltages, operating modes, and phasing may all be independently programmed over i 2 c or used in standalone mode via simple i/o with power-up defaults. the dc/dcs may be used independently or in parallel to achieve higher output currents of up to 4a per output with a shared inductor. alarm levels for high die temperature may also be programmed via i 2 c with a mask - able irq output for monitoring dc/dc and system faults. pushbutton on/off/reset control, power -on reset, and a watchdog timer provide flexible and reliable power-up sequencing and system monitoring. the ltc3375 is avail - able in a low profile 48-lead 7mm 7mm qfn package. 8-channel 1a multioutput buck regulator buck efficiency vs load a pplica t ions n 8-channel independent step-down dc/dcs n master-slave configurable for up to 4a per output channel with a single inductor n independent v in supply for each dc/dc (2.25v to 5.5v) n all dc/dcs have 0.425v to v in output voltage range n precision enable pin thresholds for autonomous sequencing (or i 2 c control) n 1mhz to 3mhz programmable/synchronizable oscillator frequency (2mhz default) n i 2 c selectable phasing (90 steps) per channel n programmable power-on reset/w atch dog/ pushbutton timing n die temperature monitor output n 48-lead (7mm 7mm) qfn package n general purpose multichannel power supplies n industrial/automotive/communications l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 0.425v to v in1 up to 1a sw1 fb1 v in1 sw2 fb2 v in2 sw7 fb7 v in7 sw8 fb8 v in8 v shnt v cc fbv cc on pb 4v to 40v always-on ldo 0.425v to v in2 up to 1a slave master slave master slave master kill pb en1 en2 en3 en4 en5 en6 en7 en8 rst temp wdi wd0 irq i 2 c sync 2 0.425v to v in7 up to 1a 0.425v to v in8 up to 1a rt ltc3375 ct 3375 ta01a ? ? ? load current (ma) 1 10 40 efficiency (%) 50 60 70 80 100 1000 3375 ta01b 30 20 10 0 90 100 burst mode operation v in = 3.3v v out = 1.8v f osc = 2mhz l = 2.2h quad buck triple buck dual buck single buck ltc3375 3375fa
2 for more information www.linear.com/3375 table o f c on t en t s features ..................................................... 1 applications ................................................ 1 t ypical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 3 order information .......................................... 3 pin configuration .......................................... 3 electrical characteristics ................................. 4 t ypical performance characteristics ................... 7 pin functions .............................................. 12 block diagram ............................................. 15 operation ................................................... 16 buck switching regulators ..................................... 16 b uck regulators with combined power stages ...... 16 p ushbutton interface .............................................. 17 p ower-up and power-down via pushbutton ........... 17 p ower-up and power-down via enable pin or i 2 c .. 19 i 2 c interface ........................................................... 20 i 2 c bus speed ......................................................... 20 i 2 c start and stop conditions ................................. 20 i 2 c byte format ...................................................... 20 i 2 c acknowledge .................................................... 20 i 2 c slave address ................................................... 21 i 2 c sub-addressed writing ..................................... 22 i 2 c bus write operation ......................................... 22 i 2 c bus read operation .......................................... 22 e rror condition reporting via rst and irq pins .... 22 te mperature monitoring and overtemperature protection ................................... 23 r eset_all functionality ....................................... 24 p rogramming the operating frequency .................. 24 v cc shunt regulator ............................................... 25 wa tchdog timer ..................................................... 25 applications information ................................ 26 b uck switching regulator output voltage and feedback network .................................................. 26 bu ck regulators ..................................................... 26 c ombined buck regulators ..................................... 26 v cc shunt regulator ............................................... 28 in put and output decoupling capacitor selection .. 29 choosing the c t capacitor ...................................... 29 pr ogramming the global register ........................... 29 p rogramming the rst and irq mask registers ..... 29 s tatus byte read back ........................................... 29 p cb considerations ................................................ 31 t ypical applications ...................................... 32 package description ..................................... 35 t ypical application ....................................... 36 related parts .............................................. 36 ltc3375 3375fa
3 for more information www.linear.com/3375 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in1-8 , fb1-8, en1-8, v cc , v shnt , fbv cc , ct, on, kill , irq , rst , pb , wdi, wdo, sync, rt, sda, scl ..................................................... C 0.3v to 6v temp ................... C 0.3v to lesser of (v cc + 0.3v) or 6v i irq , i rst , i wdo , i on ................................................. 5ma i vshnt ...................................................................... 3ma o perating junction temperature range (notes 2, 3) ............................................ C 40c to 150c storage temperature range .................. C 65c to 150c (note 1) top view gnd 49 uk package 48-lead (7mm 7mm) plastic qfn fb1 1 v in1 2 sw1 3 sw2 4 v in2 5 fb2 6 fb3 7 v in3 8 sw3 9 sw4 10 v in4 11 fb4 12 36 fb8 35 v in8 34 sw8 33 sw7 32 v in7 31 fb7 30 fb6 29 v in6 28 sw6 27 sw5 26 v in5 25 fb5 48 en1 47 en2 46 sda 45 scl 44 temp 43 v shnt 42 fbv cc 41 v cc 40 wdi 39 wdo 38 en7 37 en8 en4 13 en3 14 irq 15 rst 16 ct 17 sync 18 rt 19 on 20 pb 21 kill 22 en6 23 en5 24 t jmax = 150c, v ja = 34c/w exposed pad (pin 49) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3375euk#pbf ltc3375euk#trpbf ltc3375uk 48-lead (7mm w 7mm) plastic qfn C40c to 125c ltc3375iuk#pbf ltc3375iuk#trpbf ltc3375uk 48-lead (7mm w 7mm) plastic qfn C40c to 125c ltc3375huk#pbf ltc3375huk#trpbf ltc3375uk 48-lead (7mm w 7mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc3375 3375fa
4 for more information www.linear.com/3375 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = v in1-8 = 3.3v, unless otherwise specified. symbol parameter conditions min typ max units v vcc v cc voltage range l 2.7 5.5 v v vcc_uvlo undervoltage threshold on v cc v cc voltage falling v cc voltage rising l l 2.35 2.45 2.45 2.55 2.55 2.65 v v i vcc_alloff v cc input supply current all switching regulators in shutdown, pb = high 11 25 a i vcc v cc input supply current at least 1 buck active, sync = 0v, r t = 400k, v fb_buck = 0.85v at least 1 buck active, sync = 2mhz 50 200 85 325 a a f osc internal oscillator frequency v rt = v cc , sync = 0v v rt = v cc , sync = 0v r rt = 400k, sync = 0v l l 1.8 1.75 1.8 2 2 2 2.2 2.25 2.2 mhz mhz mhz f sync synchronization frequency t low , t high > 40ns 1 3 mhz v sync sync level high sync level low l l 1.2 0.4 v v v rt rt servo voltage r rt = 400k l 780 800 820 mv temperature monitor v temp(room) temp voltage at 25c 150 mv ?v temp /c v temp slope l 6.75 mv/c ot overtemperature shutdown temperature rising 165 c ot_hyst overtemperature hysteresis 10 c dt_warn die temperature warning threshold (die temperature that causes irq = 0) dt[1], dt[0] = 00 dt[1], dt[0] = 01 dt[1], dt[0] = 10 dt[1], dt[0] = 11 inactive 140 125 110 c c c 1a buck regulators v buck buck input voltage range l 2.25 5.5 v v out l v fb v in v v in_uvlo undervoltage threshold on v in v in voltage falling v in voltage rising l l 1.95 2.05 2.05 2.15 2.15 2.25 v v i vin_buck burst mode ? operation forced continuous mode operation shutdown input current shutdown input current v fb_buck = 0.85v (note 4) i sw_buck = 0a, v fb_buck = 0v all switching regulators in shutdown at least one other buck active 18 400 0 1 50 550 1 2 a a a a i fwd pmos current limit (note 5) 2.0 2.3 2.7 a v fb (default) feedback regulation voltage forced continuous mode default (1, 1, 0, 0) l 705 725 745 mv v fb (high) feedback regulation voltage forced continuous mode full scale (1, 1, 1, 1) l 780 800 820 mv v fb (low) feedback regulation voltage forced continuous mode zero scale (0, 0, 0, 0) l 405 425 445 mv v lsb v fb servo voltage step size 25 mv i fb feedback leakage current v fb_buck = 0.85v C50 50 na dmax maximum duty cycle v fb_buck = 0v l 100 % r pmos pmos on-resistance i sw_buck = 100ma 265 m r nmos nmos on-resistance i sw_buck = C100ma 280 m i leakp pmos leakage current en_buck = 0 C2 2 a i leakn nmos leakage current en_buck = 0 C2 2 a r swpd output pull-down resistance in shutdown en_buck = 0 (i 2 c bit set) 1 k t ss soft-start time default (1, 1, 0, 0) reference voltage 1 ms ltc3375 3375fa
5 for more information www.linear.com/3375 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = v in1-8 = 3.3v, unless otherwise specified. symbol parameter conditions min typ max units v pgood(fall) falling pgood threshold voltage full-scale (1, 1, 1, 1) reference voltage 92.5 % v pgood(hys) pgood hysteresis 1 % buck regulators combined i fwd2 pmos current limit 2 buck converters combined (note 5) 4.6 a i fwd3 pmos current limit 3 buck converters combined (note 5) 6.9 a i fwd4 pmos current limit 4 buck converters combined (note 5) 9.2 a v cc regulator v fbvcc fbv cc regulation voltage 1.17 1.2 1.23 v r reg pull-down resistance for v cc (regulator) 200 v vshnt_max v shnt clamp voltage i shnt = 2ma, fbv cc = 0v 6.1 v r clamp pull-down resistance for v shnt (clamp) 200 i 2 c port address i 2 c address l 0110100[r/wb] v ih input high voltage sda/scl l 1.2 v v il input low voltage sda/scl l 0.4 v i ih input high current sda/scl 50 na i il input low current sda/scl 50 na v ol_sda sda output low voltage i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sda hold time after repeated start condition 0.6 s t su_sta repeated start condition set-up time 0.6 s t su_sto stop condition set-up time 0.6 s t hd_dat(o) data hold time output 0 900 ns t hd_dat(i) data hold time input 0 ns t su_dat data set-up time 250 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f clock/data fall time c b = capacitance of one bus line (pf) 20+0.1c b 300 ns t r clock/data rise time c b = capacitance of one bus line (pf) 20+0.1c b 300 ns interface logic pins (on, kill, rst, irq, pb, wdi, wdo) i oh output high leakage current on, rst, irq, wdo 5.5v at pin -1 1 a v ol output low voltage on, rst, irq, wdo 3ma into pin 0.1 0.4 v v ih input high threshold kill, pb, wdi l 1.2 v v il input low threshold kill, pb, wdi l 0.4 mv t wdi time from last wdi 1.5 sec t wdo wdo low time absent a transition at wdi 200 ms t wdreset time from a wdi transition until the wd timer is reset 2 s ltc3375 3375fa
6 for more information www.linear.com/3375 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = v in1-8 = 3.3v, unless otherwise specified. symbol parameter conditions min typ max units interface logic pins (en1, en2, en3, en4, en5, en6, en7, en8) v hi_alloff enable rising threshold all regulators disabled l 400 730 1200 mv v en_hys enable hysteresis 60 mv v hi enable rising threshold at least one regulator enabled l 380 400 420 mv i en enable pin leakage current en = v cc = v in = 5.5v C1 1 a pushbutton parameters, c t = 0.01f t pb_lo pb low time to irq low on high 28 50 72 ms t pb_on pb low time to on high 140 200 260 ms t pb_off pb low to on forced low 7 10 13 sec t hr time for which all enabled regulators are disabled after kill is asserted high on high 0.7 1 1.3 sec t irq _pw irq minimum pulse width on high 28 50 72 ms t killh time in which kill must be asserted high after on rising edge 7 10 13 sec t killl kill low time to on low on high 28 50 72 ms t rst rst assertion delay 160 230 300 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3375 is tested under pulsed load conditions such that t j t a . the ltc3375e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3375i is guaranteed over the C40c to 125c operating junction temperature range. the ltc3375h is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: the ltc3375 includes overtemperature protection which protects the device during momentary overload conditions. junction temperatures will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: static current, switches not switching. actual current may be higher due to gate charge losses at the switching frequency. note 5: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum specified pin current rating may result in device degradation over time. ltc3375 3375fa
7 for more information www.linear.com/3375 typical p er f or m ance c harac t eris t ics v cc supply current vs temperature v cc supply current vs temperature rt programmed oscillator frequency vs temperature default oscillator frequency vs temperature oscillator frequency vs v cc oscillator frequency vs r t v cc undervoltage threshold vs temperature buck v in undervoltage threshold vs temperature v cc supply current vs temperature temperature (c) ?50 uv threshold (v) 2.50 2.60 150 3375 g01 2.40 2.30 0 50 100 ?25 25 75 125 2.70 2.45 2.55 2.35 2.65 v cc rising v cc falling temperature (c) ?50 uv threshold (v) 2.10 2.20 150 3375 g02 2.00 1.90 0 50 100 ?25 25 75 125 2.30 2.05 2.15 1.95 2.25 v in rising v in falling temperature (c) ?50 i vcc_alloff (a) 30 45 50 150 3375 g03 25 20 0 0 50 100 ?25 25 75 125 10 60 55 40 35 15 5 all regulators in shutdown v cc = 5.5v v cc = 3.3v v cc = 2.7v temperature (c) ?50 f osc (mhz) 1.95 2.10 150 3375 g06 1.85 1.80 0 50 100 ?25 25 75 125 2.20 1.90 2.00 2.05 2.15 v cc = 5.5v v cc = 3.3v v cc = 2.7v r rt = 400k temperature (c) ?50 f osc (mhz) 1.95 2.10 150 3375 g07 1.85 1.80 0 50 100 ?25 25 75 125 2.20 1.90 2.00 2.05 2.15 v cc = 5.5v v cc = 3.3v v cc = 2.7v v rt = v cc v cc (v) 2.7 f osc (mhz) 1.95 2.10 5.5 3375 g08 1.85 1.80 3.5 4.3 5.1 3.1 3.9 4.7 2.20 1.90 2.00 2.05 2.15 v rt = v cc r rt = 400k r rt (k) 250 f osc (mhz) 2.0 2.5 3.0 650 750700 3375 g09 1.5 1.0 0 350 450 550 300 800 400 500 600 0.5 4.0 3.5 v cc = 3.3v temperature (c) ?50 i vcc (a) 100 150 3375 g04 50 0 0 50 100 ?25 25 75 125 25 125 75 v cc = 5.5v v cc = 3.3v v cc = 2.7v at least one buck enabled sync = 0v fb = 850mv temperature (c) ?50 i vcc (a) 320 280 150 3375 g05 160 120 0 0 50 100 ?25 25 75 125 80 40 400 360 240 200 v cc = 5.5v v cc = 3.3v v cc = 2.7v at least one buck enabled sync = 2mhz ltc3375 3375fa
8 for more information www.linear.com/3375 typical p er f or m ance c harac t eris t ics enable pin precision threshold vs temperature temperature (c) ?50 en threshold (mv) 395 410 150 3375 g12 385 380 0 50 100 ?25 25 75 125 420 390 400 405 415 en rising en falling enable threshold vs temperature v temp vs temperature buck v in supply current vs temperature pmos current limit vs temperature pmos r ds(on) vs temperature nmos r ds(on) vs temperature buck v in supply current vs temperature v out vs temperature temperature (c) ?50 400 en threshold (mv) 450 550 600 650 900 750 0 50 75 3375 g11 500 800 850 700 ?25 25 100 125 150 all regulators disabled v cc = 3.3v en rising en falling 0 ?200 v temp (mv) 0 400 1400 800 20 10080 200 1000 1200 600 40 60 120 140 all regulators disabled v cc = 3.3v actual v temp ideal v temp temperature (c) 3375 g10 temperature (c) ?50 i vin_burst (a) 40 150 3375 g13 10 0 1251007550250?25 50 20 30 burst mode operation fb = 850mv v in = 5.5v v in = 2.25v v in = 3.3v temperature (c) ?50 i vin_forced_continuous (a) 450 500 150 3375 g14 50 100 150 0 1251007550250?25 550 200 250 300 350 400 forced continuous mode fb = 0v v in = 5.5v v in = 2.25v v in = 3.3v temperature (c) ?50 v out (v) 1.84 1.86 150 3375 g15 1.72 1251007550250?25 1.88 1.74 1.76 1.78 1.8 1.82 forced continuous mode load = 0ma v in = 5.5v v in = 2.25v v in = 3.3v temperature (c) ?50 i fwd (a) 2.5 150 3375 g16 2.1 2.2 2 1251007550250?25 2.6 2.3 2.4 v in = 3.3v temperature (c) ?50 r ds(on) (m) 550 500 150 3375 g17 250 300 350 200 1251007550250?25 600 400 450 v in = 2.25v v in = 3.3v v in = 5.5v temperature (c) ?50 r ds(on) (m) 550 500 150 3375 g18 250 300 350 200 1251007550250?25 600 400 450 v in = 2.25v v in = 3.3v v in = 5.5v ltc3375 3375fa
9 for more information www.linear.com/3375 typical p er f or m ance c harac t eris t ics 2a buck efficiency vs i load 2a buck efficiency vs i load 3a buck efficiency vs i load 3a buck efficiency vs i load 4a buck efficiency vs i load 1a buck efficiency vs i load 1a buck efficiency vs i load burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g21 30 20 10 0 100 10 100 40 60 70 90 v out = 1.8v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.25v v in = 5.5v v in = 3.3v v in = 2.25v forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g22 30 20 10 0 100 10 100 40 60 70 90 v out = 2.5v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.7v v in = 5.5v v in = 3.3v v in = 2.7v forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g23 30 20 10 0 100 10 100 40 60 70 90 v out = 1.8v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.25v v in = 5.5v v in = 3.3v v in = 2.25v forced continuous mode burst mode operation v out = 1.8v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.25v v in = 5.5v v in = 3.3v v in = 2.25v forced continuous mode load current(ma) 1 efficiency (%) 50 80 1000 3375 g25 30 20 10 0 100 10 100 40 60 70 90 forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g24 30 20 10 0 100 10 100 40 60 70 90 v out = 2.5v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.7v v in = 5.5v v in = 3.3v v in = 2.7v v out = 2.5v f osc = 2mhz l = 2.2h forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g26 30 20 10 0 100 10 100 40 60 70 90 v in = 3.3v v in = 5.5v v in = 2.7v v in = 5.5v v in = 3.3v v in = 2.7v v in = 3.3v v in = 5.5v v in = 2.25v v in = 5.5v v in = 3.3v v in = 2.25v v out = 1.8v f osc = 2mhz l = 2.2h forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g27 30 20 10 0 100 10 100 40 60 70 90 v cc vs temperature v shnt clamp voltage vs temperature temperature (c) ?50 3.20 v cc (v) 3.22 3.26 3.28 3.30 3.40 3.34 0 50 75 3375 g19 3.24 3.36 3.38 3.32 ?25 25 100 125 150 for v cc feedback divider r top = 187k r bot = 107k temperature (c) ?50 v shnt clamp voltage (v) 6.18 6.12 6.14 6.16 150 3375 g20 6.02 6.04 6.06 6.00 1251007550250?25 6.20 6.08 6.10 ltc3375 3375fa
10 for more information www.linear.com/3375 typical p er f or m ance c harac t eris t ics 1a buck regulator load regulation (forced continuous mode) 4a buck regulator load regulation (forced continuous mode) 1a buck regulator line regulation (forced continuous mode) 1a buck regulator no load startup transient (burst mode) 4a buck regulator no load startup transient (forced continuous mode) 1a buck efficiency vs frequency (forced continuous mode) 1a buck efficiency vs frequency (forced continuous mode) 1a buck efficiency vs i load (across operating frequency) v in = 2.25v v in = 3.3v v in = 5.5v frequency (mhz) 1 efficiency (%) 50 80 3 3375 g29 30 20 10 0 1.8 2.2 2.6 1.2 21.61.4 2.4 2.8 100 40 60 70 90 v out = 1.8v i l = 100ma l = 3.3h burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g31 30 20 10 0 100 10 100 40 60 70 90 v out = 1.8v v in = 3.3v f osc = 2mhz, l = 2.2h f osc = 3mhz, l = 1h f osc = 1mhz, l = 3.3h f osc = 3mhz, l = 1h f osc = 2mhz, l = 2.2h f osc = 1mhz, l = 3.3h forced continuous mode i l = 100ma i l = 500ma i l = 20ma frequency (mhz) 1 efficiency (%) 50 80 3 3375 g30 30 20 10 0 1.4 1.8 2.4 2.6 1.2 1.6 2 2.2 2.8 100 40 60 70 90 v out = 1.8v v in = 3.3v l = 3.3h v in = 5.5v dropout v in = 3.3v v in = 2.25v i l (ma) 1 v out (v) 1.8 1.812 1000 3375 g32 1.792 1.788 1.784 1.78 100 10 1.82 1.796 1.804 1.808 1.816 f osc = 2mhz l = 2.2h v in = 5.5v dropout v in = 3.3v v in = 2.25v i l (ma) 1 v out (v) 1.8 1.812 1000 3375 g33 1.792 1.788 1.784 1.78 100 10 1.82 1.796 1.804 1.808 1.816 f osc = 2mhz l = 2.2h i l = 100ma i l 500ma v in (v) 2.25 2.75 v out (v) 1.81 5.25 4.25 4.75 3375 g34 1.79 1.785 1.78 3.753.25 1.82 1.795 1.8 1.805 1.815 f osc = 2mhz l = 2.2h 200s/div v out 500mv/div en 2v/div inductor current 500ma/div 3375 g35 200s/div v out 500mv/div en 2v/div inductor current 500ma/div 3375 g36 4a buck efficiency vs i load v out = 2.5v f osc = 2mhz l = 2.2h v in = 3.3v v in = 5.5v v in = 2.7v v in = 5.5v v in = 3.3v v in = 2.7v forced continuous mode burst mode operation load current(ma) 1 efficiency (%) 50 80 1000 3375 g28 30 20 10 0 100 10 100 40 60 70 90 ltc3375 3375fa
11 for more information www.linear.com/3375 typical p er f or m ance c harac t eris t ics 1a buck regulator, transient response (forced continuous mode) 4a buck regulator, transient response (forced continuous mode) 4a buck regulator, transient response (burst mode) 50s/div v out 100mv/div ac-coupled 0ma inductor current 200ma/div load step = 100ma to 700ma v in = 3.3v, v out = 1.8v 3375 g38 50s/div v out 100mv/div ac-coupled 0ma inductor current 1a/div load step = 100ma to 2.8a v in = 3.3v, v out = 1.8v 3375 g39 50s/div v out 100mv/div ac-coupled 0ma inductor current 1a/div load step = 400ma to 2.8a v in = 3.3v, v out = 1.8v 3375 g40 1a buck regulator, transient response (burst mode) 50s/div v out 100mv/div ac-coupled 0ma inductor current 200ma/div load step = 100ma to 700ma v in = 3.3v, v out = 1.8v 3375 g37 ltc3375 3375fa
12 for more information www.linear.com/3375 p in func t ions fb1 (pin 1): buck regulator 1 feedback pin. receives feedback by a resistor divider connected across the output. v in1 (pin 2): buck regulator 1 input supply. bypass to gnd with a 10f or larger ceramic capacitor. sw1 (pin 3): buck regulator 1 switch node. external inductor connects to this pin. sw2 (pin 4): buck regulator 2 switch node. external inductor connects to this pin. v in2 (pin 5): buck regulator 2 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in1 when buck regulator 2 is combined with buck regulator 1 for higher current. fb2 (pin 6): buck regulator 2 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb2 to v in2 combines buck regulator 2 with buck regulator 1 for higher current. up to 4 converters may be combined in this way. fb3 (pin 7): buck regulator 3 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb3 to v in3 combines buck regulator 3 with buck regulator 2 for higher current. up to 4 converters may be combined in this way. v in3 (pin 8): buck regulator 3 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in2 when buck regulator 3 is combined with buck regulator 2 for higher current. sw3 (pin 9): buck regulator 3 switch node. external inductor connects to this pin. sw4 (pin 10): buck regulator 4 switch node. external inductor connects to this pin. v in4 (pin 11): buck regulator 4 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in3 when buck regulator 4 is combined with buck regulator 3 for higher current. fb4 (pin 12): buck regulator 4 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb4 to v in4 combines buck regulator 4 with buck regulator 3 for higher current. up to 4 converters may be combined in this way. en4 (pin 13): buck regulator 4 enable input. active high. en3 (pin 14): buck regulator 3 enable input. active high. irq (pin 15): interrupt pin (active low). open-drain output. when an undervoltage, die temperature, or unmasked error condition is detected, this pin is driven low. rst (pin 16): reset pin (active low). open-drain output. when the regulated output voltage of any unmasked enabled switching regulator is more than 7.5% below its programmed level, this pin is driven low. assertion delay is scaled by the c t capacitor. when all buck regulators are disabled rst is driven low. ct (pin 17): timing capacitor pin. a capacitor connected to gnd sets a time constant which is scaled for use by the on, kill, pb, rst and irq pins. sync (pin 18): oscillator synchronization pin. driving sync with an external clock signal will synchronize all switchers to the applied frequency. the slope compensation is automatically adapted to the external clock frequency. the absence of an external clock signal will enable the frequency programmed by the rt pin. do not float. rt (pin 19): oscillator frequency pin. this pin provides two modes of setting the switching frequency. connecting a resistor from rt to ground will set the switching frequency based on the resistor value. if rt is tied to v cc the default ltc3375 3375fa
13 for more information www.linear.com/3375 p in func t ions internal 2mhz oscillator will be used. do not float. on (pin 20): open-drain output. when the pb pin is pressed and released, the signal is debounced and the on signal is held high for a minimum time period that is scaled by the c t capacitor. on is forced low if: a) kill is not driven high (by p) within 10 seconds of the initial valid pb power turn-on event, b) kill is driven low during normal operation, c) pb is pressed and held low for 10 seconds during normal operation, d) a reset_all i 2 c command is written. this pin can connect directly to a dc/dc converter enable pin that provides an internal pull- up. other wise a pull-up resistor to an external supply is required. all associated times are scaled by the c t capacitor. pb (pin 21): pushbutton input. active low. pb is internally pulled to v cc through a 420k (typical) resistor. kill (pin 22): kill input pin. forcing kill low releases the on output which in turn is forced low. while kill is low, the buck converters will be forced to power down and will remain powered down for 1 second (scaled by the c t capacitor) after kill returns high. during system turn- on, this pin is blanked by a 10 second (scaled by the c t capacitor) (t killh ) to allow the system to pull kill high. if unused, connect to v cc . en6 (pin 23): buck regulator 6 enable input. active high. en5 (pin 24): buck regulator 5 enable input. active high. fb5 (pin 25): buck regulator 5 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb5 to v in5 combines buck regulator 5 with buck regulator 4 for higher current. up to 4 converters may be combined in this way. v in5 (pin 26): buck regulator 5 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in4 when buck regulator 5 is combined with buck regulator 4 for higher current. sw5 (pin 27): buck regulator 5 switch node. external inductor connects to this pin. sw6 (pin 28): buck regulator 6 switch node. external inductor connects to this pin. v in6 (pin 29): buck regulator 6 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in5 when buck regulator 6 is combined with buck regulator?5 for higher current. fb6 (pin 30): buck regulator 6 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb6 to v in6 combines buck regulator 6 with buck regulator 5 for higher current. up to 4 converters may be combined in this way. fb7 (pin 31): buck regulator 7 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb7 to v in7 combines buck regulator 7 with buck regulator 6 for higher current. up to 4 converters may be combined in this way. v in7 (pin 32): buck regulator 7 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in6 when buck regulator 7 is combined with buck regulator 6 for higher current. sw7 (pin 33): buck regulator 7 switch node. external inductor connects to this pin. sw8 (pin 34): buck regulator 8 switch node. external inductor connects to this pin. v in8 (pin 35): buck regulator 8 input supply. bypass to gnd with a 10f or larger ceramic capacitor. may be driven by an independent supply or must be shorted to v in7 when buck regulator 8 is combined with buck regulator 7 for higher current. fb8 (pin 36): buck regulator 8 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb8 to v in8 combines buck regulator 8 with buck regulator 7 for higher current. up to 4 converters may be combined in this way. ltc3375 3375fa
14 for more information www.linear.com/3375 p in func t ions en8 (pin 37): buck regulator 8 enable input. active high. en7 (pin 38): buck regulator 7 enable input. active high. wdo (pin 39): watchdog timer output. open-drain output. wdo is pulled low for 200ms during a watchdog timer failure. wdi (pin 40): watchdog timer input. the wdi pin must be toggled either low to high or high to low every 1.5 seconds. failure to toggle wdi results in the wdo pin being pulled low for 200ms. v cc (pin 41): always-on ldo output voltage/internal bias supply. when used as a regulator, v cc should be connected to the emitter/source of the external ldo npn/ nfet transistor. v cc serves as a low voltage rail that may be used to provide power to external circuitry, and is also used to power the internal top level circuitry of the ltc3375. alternatively the v cc pin may be connected to a 2.7v to 5.5v external power supply. in this case fbv cc and v shnt should be tied to ground. fbv cc (pin 42): always-on ldo feedback pin. receives feedback by a resistor divider connected across v cc . v shnt (pin 43): shunt regulator base control voltage. v shnt should be connected to the base/gate of an external high voltage npn/nfet transistor and to its collector/drain through a resistor. temp (pin 44): temperature indication pin. temp out- puts a voltage of 150mv (typical) at room temperature. the temp voltage will change by 6.75mv/c (typical) giving an external indication of the ltc3375 internal die temperature. scl (pin 45): serial clock line for i 2 c port. sda (pin 46): serial data line for i 2 c port. open-drain output during read back. en2 (pin 47): buck regulator 2 enable input. active high. en1 (pin 48): buck regulator 1 enable input. active high. gnd (exposed pad pin 49): ground. the exposed pad must be connected to a continuous ground plane on the printed circuit board directly under the ltc3375 for electri - cal contact and rated thermal performance. ltc3375 3375fa
15 for more information www.linear.com/3375 b lock diagra m 46 45 sda scl 13 49 en4 12 fb4 10 sw4 11 v in4 14 en3 7 fb3 9 sw3 8 v in3 47 en2 6 fb2 4 sw2 master/slave lines master/slave lines master/slave lines master/slave lines gnd (exposed pad) master/slave lines master/slave lines master/slave lines 5 v in2 48 en1 1 fb1 3 sw1 ref, clk 1.2v ldo output voltage, slew control mode, phase, en, status bits 2 24 25 27 26 23 30 28 29 38 31 33 32 37 36 34 35 v in1 en5 3375 bd fb5 sw5 v in5 en6 fb6 sw6 v in6 en7 fb7 sw7 v in7 en8 fb8 sw8 v in8 39 40 21 17 20 22 15 16 wdo wdi pb ct on kill irq rst buck regulator 4 1a buck regulator 3 1a buck regulator 2 1a buck regulator 1 1a buck regulator 5 1a buck regulator 6 1a buck regulator 7 1a buck regulator 8 1a bandgap, oscillator, uv, ot temp monitor top logic, ct oscillator timing 19 rt 18 sync 44 temp + ? 42 fbv cc 43 v shnt 41 v cc i 2 c ltc3375 3375fa
16 for more information www.linear.com/3375 o pera t ion buck switching regulators the ltc3375 contains eight monolithic 1a synchronous buck switching regulators. all of the switching regulators are internally compensated and need only external feedback resistors to set the output voltage. the switching regula - tors offer two operating modes: burst mode operation (power -up default mode) for higher efficiency at light loads and for ced continuous pwm mode for lower noise at light loads. in burst mode operation at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. the regulator then goes into sleep mode, during which time the output capacitor provides the load current. in sleep most of the regulators circuitry is powered down, helping conserve input power. when the output capacitor droops below its programmed value, the circuitry is powered on and another burst cycle begins. the sleep time decreases as load current increases. in burst mode operation, the regulator will burst at light loads whereas at higher loads it will operate at constant frequency pwm mode operation. in forced continuous mode (selectable via i 2 c command), the oscillator runs continuously and the buck switch currents are allowed to reverse under very light load conditions to maintain regulation. this mode allows the buck to run at a fixed frequency with minimal output ripple. each buck switching regulator has its own v in , sw, fb and en pin to maximize flexibility. the enable pins have two different enable threshold voltages that depend on the operating state of the ltc3375. with all regulators disabled, the enable pin threshold is set to 730mv (typical). once any regulator is enabled, the enable pin thresholds of the remaining regulators are set to a bandgap-based 400mv and the en pins are each monitored by a precision comparator. this precision en threshold may be used to provide event-based sequencing via feedback from other previously enabled regulators. all buck regulators have forward and reverse-current limiting, soft-start to limit inrush current during start-up, and short-circuit protection. each buck can operate in standalone mode using the en pin in its default mode and fb reference settings, or be fully controlled using the i 2 c port. i 2 c commands may be used to independently program each buck regulators operating mode, oscillator phase, and reference voltage in addition to simple on/off control. each buck may have its phase programmed in 90 phase steps via i 2 c. the phase step command programs the fixed edge of the switching sequence, which is when the pmos turns on. the pmos off (nmos on) phase is subject to the duty cycle demanded by the regulator. bucks 1 and 2 default to 0, bucks 3 and?4 default to 90, bucks 5 and 6 default to 180, and bucks?7 and 8 default to 270. each buck can have its feedback voltage independently programmed in 25mv increments from 425mv to 800mv. all regulators feedback voltages default to 725mv at initial power-up. in cases where power stages are combined, the register content of the master program the combined buck regulators behavior and the register contents of the slave are ignored. two additional i 2 c commands act on all the buck switch - ing regulators together. in shutdown, an i 2 c control bit keeps all the sw nodes in a high impedance state (default) or forces all the sw nodes to decay to gnd through 1k (typical) resistors. also, the slew rate of the sw nodes may be switched from the default value to a lower value for reduced radiated emi at the cost of a small drop in efficiency. each buck regulator may be enabled via its enable pin or i 2 c. the buck regulator enable pins may be tied to v out voltages, through a resistor divider, to program power- up sequencing. if a different power-down sequence is required, the enables can be redundantly written via i 2 c. the en pins can then be ignored via an i 2 c command, and the switching regulators may be powered down via i 2 c while the en pins remain tied to the output voltages of other regulators. in addition to many programming options, there are also 17 bits of data that may be read back to report fault condi - tions on the ltc3375, and all i 2 c commands can be read back prior to executing. buck regulators with combined power stages up to four adjacent buck regulators may be combined in a master-slave configuration by connecting their sw pins together, connecting their v in pins together, and connecting the higher numbered bucks fb pin(s) to the input supply. the lowest numbered buck is always the master. in figure?1, buck regulator 1 is the master. the ltc3375 3375fa
17 for more information www.linear.com/3375 o pera t ion feedback network connected to the fb1 pin programs the output voltage to 1.2v. the fb2 pin is tied to v in1/2 , which configures buck regulator 2 as the slave. the sw1 and sw2 pins must be tied together, as must the v in1 and v in2 pins. the register contents of the master program, the combined buck regulators behavior, and the register contents of the slave are ignored. the slave buck control circuitry draws no current. the enable of the master buck (en1) controls the operation of the combined bucks; the enable of the slave regulator (en2) must be tied to ground. any combination of 2, 3, or 4 adjacent buck regulators may be combined to provide either 2a, 3a, or 4a of aver - age output load current. for example, buck regulator 1 and buck regulator 2 may run independently , while buck regulators 3 and 4 may be combined to provide 2a, while buck regulators 5 through 8 may be combined to provide 4a. buck regulator 1 is never a slave, and buck regulator? 8 is never a master. 15 unique output power stage configu - rations are possible to maximize application flexibility. the ltc3375 is in an off state when it is powered up with all regulators in shutdown. the on pin is low in the off state. the on pin will go high if pb is pulled low for 200ms. the on pin stays in its high state for 10 seconds and then returns low unless kill is asserted high in this time in which case on will remain high. if kill goes low, for longer than a 50ms debounce time, while on is high after the 10 second time has expired, on will again go to its low state. pb being held low causes the kill pin to be ignored. once in the on state (on pin is high), the ltc3375 can be powered down in one of three ways that allow for flex - ibility between hardware and software system resets. first, if pb is held low for at least 10 seconds, then on will be driven low. this will not force a hard reset on any of the buck switching regulators. the on pin, however, may be used to either drive the en pin of the first sequenced buck converter or that of an upstream high voltage buck switching regulator. in this case the irq pin is latched to its low state to indicate a pb induced reset. second, if the pb pin is driven low for longer than 50ms but less than 10 seconds, the irq pin will be pulled low for as long as the pb pin remains low. if a microcontroller sees a transient irq low signal, then this should signal that the user has pressed the pb . a software power-down may then be initiated if so desired. finally, if the kill input is driven low for longer than 50ms, then a hard reset will be initiated. all enabled buck switching regulators will be turned off while kill is low and will remain powered down for 1 second after kill returns high. kill being low also forces a hard reset while the pushbutton is in the off state. a hard reset may also be generated by using the reset_all i 2 c command that will last for 1 second. the pushbutton will return to the off state. kill must be high to power-up using en pins or i 2 c. in any hard reset event all buck regulator i 2 c bits are set low. power-up and power-down via pushbutton the ltc3375 may be turned on and off using the pb, kill, and on pins as shown in figures 2a and 2b. in figures?2a and 2b, pressing pb low at time t 1 , causes the on pin to go high at time t 2 and stay high for at least 10 seconds after which on will go low unless kill has been asserted high. on can be connected to the en pin buck regulator 1 (master) v in v in sw1 c out v out 1.2v 2a 475k l1 725k fb1 en1 v in1 buck regulator 2 (slave) sw2 en2 fb2 3375 f01 v in2 figure 1. buck regulators configured as master-slave pushbutton interface the ltc3375 includes a pushbutton interface which can be used to provide power-up or power-down control for either the part or the application. the pb, kill, and on pins provide the user with flexibility to power-up or power-down the part in addition to having i 2 c control. all pb timing parameters are scaled using the ct pin. times described below apply to a nominal c t capacitor of 0.01f. ltc3375 3375fa
18 for more information www.linear.com/3375 o pera t ion pb kill = 0 buck1-buck8 hard reset sequence up t 1 t 2 t 3 3375 f02a sequence down kill not asserted before t 3 on (tied to en1) t pb_on t killh pb kill irq buck1-buck8 hard reset sequence up don?t care 3375 f02b sequence down t 1 t 2 t 3 t 4 t 5 on (tied to en1) t pb_off t killh t pb_on figure 2a. power-up using pb (sequenced power-up, figure 8) figure 2b. power-up and power-down using pb (sequenced power-up, figure 8) figure 2c. power-up using pb and power-down using kill pb kill buck1-buck8 hard reset don?t care sequence up t 1 t 2 t 3 t 4 t 5 3375 f02c irq on (tied to en1) t pb_on t kill t killh ltc3375 3375fa
19 for more information www.linear.com/3375 o pera t ion of either an upstream high voltage buck regulator, or any en pin causing its associated buck switching regulator to power-up, which can sequentially power-up the other buck regulators. the rst pin gets pulled high 230ms after the last enabled buck is in its pgood state. an application showing sequential regulator start-up is shown in the t ypical applications section (figure 8). in figure 2b, pb is held low at instant t 4 for 10 seconds. this causes on to return to a low state, which can se - quence a power-down by either shutting down an upstream high voltage buck, or by shutting down one of the internal buck switching regulators. in figure 2c, kill is pulled low while the pushbutton is in the on state. this causes a hard reset to be generated at t 4 , all regulators are powered down 50ms later at time t 5 . an i 2 c signaled reset will have the same effect as pulling kill low momentarily. in figure 2d, pb is held low at instant t 4 for a time greater than 50ms but less than 10 seconds. this causes a transient irq signal. this unlatched interrupt can be used to signal a user pushbutton request. in this case a software reset may be initiated if so desired. in figure 2d, the microprocessor initiates the power-down sequenc - ing after the user pushbutton signal at time t 6 . at time t 7 , once all the converters are powered down, the micro brings kill low. 50ms later at time t 8 on goes low. in this case, a hard reset is issued until 1 second after kill returns high at t 9 . none of the pushbutton based irq signals are reported in an i 2 c register. as such, any irq signals that are not revealed by polling the i 2 c read back may be interpreted as caused by the pushbutton. power-up and power-down via enable pin or i 2 c all regulators can be enabled either via its enable pin or i 2 c. if the use of the pushbutton interface is not desired pb and kill should be tied to v cc , and the user may simply enable any of the buck switching regulators by asserting a high signal on any of the en pins or by writing a buck switching regulator en command to the i 2 c. if no i 2 c en- able has been written, the buck switching regulator may be powered down by simply returning its en pin to a low state. if it is wished to power -down the converters via i 2 c, an ignore_en command may be written causing the ltc3375 to treat the state of the en pin as low regard - less of its input. then, the buck switching converters can be powered down via i 2 c regardless of their associated en pin. alternatively a reset_all command may be written that will force all the buck switching regulators to power-down and remain powered down for a minimum of one second before they are allowed to be re-enabled. pb kill irq buck1-buck8 hard reset t 1 t 2 sequence up sequence down t 3 t 4 t 5 t 6 t 7 t 8 t 9 3375 f02d on (tied to en1) <10 sec t pb_on t pb_lo t killlo t hr figure 2d. power-up using pb and power-down using a soft reset ltc3375 3375fa
20 for more information www.linear.com/3375 o pera t ion t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3375 f03 t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 1 2 3 address wr 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b figure 3. i 2 c bus operation i 2 c interface the ltc3375 may communicate with a bus master using the standard i 2 c 2-wire interface. the timing diagram (figure?3) shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the ltc3375 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the v cc supply. the i 2 c port has an undervoltage lockout on the v cc pin. when v cc is below 1.8v, the i 2 c serial port is cleared and the ltc3375 registers are set to their default configurations. i 2 c bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure cor - rect operation when addressed from the i 2 c compatible master device. i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc3375, the master may transmit a stop condition which commands the ltc3375 to act upon its new command set. a stop condition is sent by the master by transition - ing sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. i 2 c byte format each byte sent to or received from the ltc3375 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the ltc3375 most significant bit (msb) first. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the ltc3375 is written to (write address), it acknowledges its write address as well as the subsequent two data bytes. when it is read from (read address), the ltc3375 acknowledges its read address only. the bus master should acknowledge receipt of information from the ltc3375. an acknowledge (active low) generated by the ltc3375 lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the ltc3375 pulls down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. ltc3375 3375fa
21 for more information www.linear.com/3375 o pera t ion table 1. summary of i 2 c sub-addresses and byte formats. bits a7, a6, a5, a4 of sub-address need to be 0 to access registers sub-address a7a6a5a4a3a2a1a0 operation action byte format d7d6d5d4d3d2d1d0 default d7d6d5d4d3d2d1d0 comments 0000 0000 (00h) read/write global logic reset_all, dt[1], dt[0], ignore_en, 1kpd, slow, rd_temp, unused 0000 0000 bits either act at top level or on all buck switching regulators at once 0000 0001 (01h) read/write buck1 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0000 1100 0000 0010 (02h) read/write buck2 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0000 1100 0000 0011 (03h) read/write buck3 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0001 1100 0000 0100 (04h) read/write buck4 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0001 1100 0000 0101 (05h) read/write buck5 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0010 1100 0000 0110 (06h) read/write buck6 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0010 1100 0000 0111 (07h) read/write buck7 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0011 1100 0000 1000 (08h) read/write buck8 register enable, mode, phase[1], phase[0], dac[3], dac[2]. dac[1], dac[0] 0011 1100 0000 1001 (09h) read/write rst mask pgood[8], pgood[7], pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] 1111 1111 fault will pull rst low if the corresponding bit is 1 0000 1010 (0ah) read/write irq pgood mask pgood[8], pgood[7], pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] 0000 0000 fault will pull irq low if the corresponding bit is 1 0000 1011 (0bh) read/write irq uvlo mask uvlo[8], uvlo[7], uvlo[6], uvlo[5], uvlo[4], uvlo[3], uvlo[2], uvlo[1] 0000 0000 fault will pull irq low if the corresponding bit is 1 0000 1100 (0ch) read pgood status register (latched at irq fault) pgood[8], pgood[7], pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] read back of pgood based faults. if the corresponding mask bit is 0, then bit can be used to read back real time data 0000 1101 (0dh) read uvlo status register (latched at irq fault) uvlo[8], uvlo[7], uvlo[6], uvlo[5], uvlo[4], uvlo[3], uvlo[2], uvlo[1] read back of uvlo based faults. if the corresponding mask bit is 0, then bit can be used to read back real time data 0000 1110 (0eh) read temp monitor dt_warn, temp[6], temp[5], temp[4], temp[3], temp[2], temp[1], temp[0] temp bits read back the temp digital code. dt_warn bit latches high if an irq fault has been caused due to a dt warning 0000 1111 (0fh) write clear interrupt na clears the interrupt bit, status latches are unlatched when the ltc3375 is read from, it releases the sda line so that the master may acknowledge receipt of the data. since the ltc3375 only transmits one byte of data during a read cycle, a master not acknowledging the data sent by the ltc3375 has no i 2 c specific consequence on the operation of the i 2 c port. i 2 c slave address the ltc3375 responds to a 7-bit address which has been factory programmed to b0110100[r/wb]. the lsb of the address byte, known as the read/write bit, should be 0 when writing to the ltc3375 and 1 when reading data from it. considering the address as an 8-bit word, ltc3375 3375fa
22 for more information www.linear.com/3375 o pera t ion the write address is 68h and the read address is 69h. the ltc3375 will acknowledge both its read and write address. i 2 c sub-addressed writing the ltc3375 has 13 command registers for control input. they are accessed by the i 2 c port via a sub-addressed writing system. a single write cycle of the ltc3375 consists of exactly three bytes except when a clear interrupt command is written. the first byte is always the ltc3375s write address. the second byte represents the ltc3375s sub-address. the sub-address is a pointer which directs the subsequent data byte within the ltc3375. the third byte consists of the data to be written to the location pointed to by the sub-address. the ltc3375 contains 12 control registers which can be written to. i 2 c bus write operation the master initiates communication with the ltc3375 with a start condition and the ltc3375s write address. if the address matches that of the ltc3375, the ltc3375 returns an acknowledge. the master should then deliver the sub-address. again the ltc3375 acknowledges and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowledge by the ltc3375. this procedure must be repeated for each sub-address that requires new data. after one or more cycles of [address][sub-address] [data], the master may terminate the communication with a stop condition. multiple sub-addresses may be written to with a single address command using a [address][sub-address][data][sub-address] [da t a] sequence. alternatively, a repeat-start condi - tion can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue indefinitely and the ltc3375 will remember the last input valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the ltc3375 will update its command latches with the data that it had received. it is important to understand that until a stop signal is transmitted, data written to the ltc3375 command reg - isters is not acted on by the ltc3375. only once a stop signal is issued is the data transferred to the command latch and acted on. i 2 c bus read operation the ltc3375 has 13 command registers and three status registers. the contents of any of these registers, except for the clear interrupt (0fh) register, may be read back via i 2 c. to read the data of a register, that registers sub-address must be provided to the ltc3375. the bus master reads the status of the ltc3375 with a start condition followed by the ltc3375 write address followed by the first data byte (the sub-address of the register whose data needs to be read) which is acknowledged by the ltc3375. after receiving the acknowledge signal from the ltc3375 the bus master initiates a new start condition followed by the ltc3375 read address. the ltc3375 acknowledges the read address and then returns a byte of read back data from the selected register. a stop command is not required for the bus read operation. immediately after writing data to a register, the contents of that register may be read back if the bus master issues a start condition followed by the ltc3375 read address. error condition reporting via rst and irq pins error conditions are reported back via the irq and rst pins. after an error condition is detected, status data can be read back to a microprocessor via i 2 c to determine the exact nature of the error condition. figure 4 is a simplified schematic showing the signal path for reporting errors via the rst and irq pins. all buck switching regulators have an internal power good (pgood) signal. when the regulated output voltage of an enabled switcher rises above 93.5% of its programmed value, the pgood signal will transition high. when the regulated output voltage falls below 92.5% of its pro - grammed value, the pgood signal is pulled low. if any internal pgood signal is not masked and stays low for greater than 50s, then the rst and irq pins are pulled low, indicating to a microprocessor that an error condition has occurred. the 50s filter time prevents the pins from being pulled low due to a transient. ltc3375 3375fa
23 for more information www.linear.com/3375 o pera t ion an error condition that pulls the rst pin low is not latched. when the error condition goes away, the rst pin is released and is pulled high if no other error condition exists. in addition to the pgood signals of the regulators the irq pin also indicates the status of the pushbutton, die temperature, and undervoltage flags. pushbutton faults cannot be masked. a fault that causes the irq pin to be pulled low is latched with the exception of a pushbutton press that is less than 10 seconds (c t = 0.01f) while on is high. in the case of a transient pushbutton press irq will be held low for the duration of the button press latching after the 10 second power-down time has elapsed. in all other cases when the fault condition is cleared, the irq pin is still maintained in its low state. the user needs to clear the interrupt by using a clrint command. on start-up, all pgood status outputs are unmasked with respect to rst. while all pgood and uvlo status outputs are masked with respect to irq . a power-on reset will cause rst to be pulled low. once all enabled regulators have their output pgood for 230ms typical (c t = 0.01f) the rst output goes hi-z. by masking a pgood signal, the rst or irq pin will remain hi-z even though the output voltage of a regulator may be below its pgood threshold. by masking a uvlo signal, the irq pin will remain hi-z even though its associated input voltage may be below its uvlo threshold. however, when the status registers are read back, the true condi - tions of pgood and uvlo are reported. if a uvlo irq is masked but the associated pgood signal is unmasked, then the irq pin may still be pulled low due to a pgood low signal that resulted from an input uvlo. temperature monitoring and overtemperature protection t o prevent thermal damage to the ltc3375 and its sur - rounding components, the ltc3375 incorporates an overtemperature (ot) function. when the l tc3375 die temperature reaches 165c (typical) all enabled buck switching regulators are shut down and remain in shut - down until the die temperature falls to 155c (typical). the l tc3375 also has a die temperature warning function which warns a user that the die temperature has reached its programmed alarm threshold which allows the user to take any corrective action. the die temperature warning threshold is user programmable as shown in table 2. 3375 f04 rst mask register pgood comparator v out irq mask register regulator 92.5% of programmed v out other unmasked pgood outputs unmasked pgood outputs unmasked error external pull-up resistor + ? and1 and2 other unmasked errors irq status register set clr clrint external pull-up resistor irq rst v cc v cc figure 4. simplified schematic rst and irq signal path ltc3375 3375fa
24 for more information www.linear.com/3375 o pera t ion table 2. die temperature warning thresholds dt[1], dt[0] die temperature warning threshold 00 (default) inactive 01 140c 10 125c 11 110c a die temperature warning is reported to the user by pulling the irq pin low. this warning can be read back on the lsb of the temp_monitor register. the die temperature warning flag is disabled when the dt bits are set to 00 (default). the temperature may be read back by the user either digitally through the i 2 c temp_monitor register or by sampling the temp pin analog voltage. the temperature, t, indicated by the temp pin voltage is given by: t = v temp + 19mv 6.75mv ? 1 c (1) the analog voltage can be digitally polled using an internal a/d converter. in order to digitally read the temperature voltage the user should first issue a rd_temp i 2 c com- mand to tell the a/d converter to poll the temp voltage. at least 2ms after this command has been written the user may then poll the temp bits in the t emp_monitor register . the temp bits are related to the temp voltage as follows: v temp = 1.3v ? (0.08333 + 0.007161 ? d) (2) where d corresponds to the bit weight of the digital code. combining equation 1 and equation 2 yields: t = 18.86c + 1.379c ? d (3) if die temperature warning and temperature read back functionality are not desired, then the user may shut down the temperature monitor in order to lower quies - cent current (15a typical) by tying temp to v cc . in this case all enabled buck switching regulators are still shut down when the die temperature reaches 165c (typical) and remain in shutdown until the die temperature falls to 155c (typical). if none of the buck switching regulators are enabled, then the temperature monitor is also shut down to further reduce quiescent current. reset_all functionality the reset_all bit shuts down all enabled regulators (enabled either via its enable pin or i 2 c) for one second. the reset_all bit is self clearing, and all other i 2 c bits (besides the enable bits, which are set low) will remain in their previous states. the reset_all bit will also reset the pushbutton to the powered-down state. programming the operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output voltage ripple. the operating frequency for all of the ltc3375 regulators is determined by an external resistor that is connected between the rt pin and ground. the operating frequency can be calculated by using the following equation: f osc = 8 ? 10 11 ? ? hz r t (4) while the l tc3375 is designed to function with operat - ing frequencies between 1mhz and 3mhz, it has safety clamps that will prevent the oscillator from running faster than 4mhz (typical) or slower than 250khz (typical). tying the rt pin to v cc sets the oscillator to the default internal operating frequency of 2mhz (typical). the ltc3375s internal oscillator can be synchronized, through an internal pll circuit, to an external frequency by applying a square wave clock signal to the sync pin. during synchronization, the top mosfet turn-on of any buck switching regulators operating at 0 phase are locked to the rising edge of the external frequency source. all other buck switching regulators are locked to the appro - priate phase of the external frequency source (see buck switching regulators). the synchronization frequency range is 1mhz to 3mhz. ltc3375 3375fa
25 for more information www.linear.com/3375 o pera t ion after detecting an external clock on the first rising edge of the sync pin, the pll starts up at the current frequency being programmed by the rt pin. the internal pll then requires a certain number of periods to gradually settle until the frequency at sw matches the frequency and phase of sync. when the external clock is removed the ltc3375 needs approximately 5s to detect the absence of the external clock. during this time, the pll will continue to provide clock cycles before it recognizes the lack of a sync input. once the external clock removal has been identified, the oscillator will gradually adjust its operating frequency to match the desired frequency programmed at the rt pin. v cc shunt regulator the ltc3375 has the control circuitry to regulate the output of an n-type device. the circuit should be connected as shown in figures 6a and 6b. the voltage at fbv cc will servo to 1.20v and v cc can be programmed between 2.7v and 5.5v. the n-type device can be used to regulate a lower voltage at v cc while being powered from a high voltage supply. the n-type device must be chosen so that it can handle the power dissipated in regulating v cc . the internal circuitry of the ltc3375 can only pull-down on the v shnt node. a pull-up resistor is required for positive gate drive. if v cc is incorrectly programmed or a current load at v cc causes v shnt to go above 6.1v (typical), then v shnt will be internally clamped and v cc may lose regulation. if the use of the v cc regulator is not desired, then v cc should be tied to an external dc voltage source and a decoupling capacitor. fbv cc and v shnt should be tied to ground. watchdog timer the watchdog circuit monitors a microprocessors activity. the microprocessor is required to change the logic state of the wdi pin at least once every 1.5 seconds (typical) in order to clear the watchdog timer and prevent the wdo pin from signaling a timeout. the watchdog timer begins running immediately after a power-on reset. the watchdog timer will continue to run until a transition is detected on the wdi input. during this time wdo will be in a hi-z state. once the watchdog timer times out, wdo will be pulled low and the reset timer is started. wdo being pulled low may be used to force a reset on the controlling microprocessor. if no wdi transition is received when the reset timer times out, after 200ms (typical), wdo will again become hi-z and the 1.5 seconds watchdog reset time will begin again. if a transition is received on the wdi input during the watchdog timeout period, then wdo will become hi-z immediately after the wdi transition and the 1.5 seconds watchdog reset time will begin at that point. ltc3375 3375fa
26 for more information www.linear.com/3375 a pplica t ions i n f or m a t ion buck switching regulator output voltage and feedback network the output voltage of the buck switching regulators is programmed by a resistor divider connected from the switching regulators output to its feedback pin and is given by v out = v fb (1 + r2/r1) as shown in figure 5. typical values for r1 range from 40k to 1m. the buck regulator transient response may improve with optional capacitor c ff that helps cancel the pole created by the feedback resistors and the input capacitance of the fb pin. experimentation with capacitor values between 2pf and 22pf may improve transient response. figure 5. feedback components buck switching regulator v out c out (optional) c ff r2 r1 fb 3375 f05 + buck regulators all eight buck regulators are designed to be used with inductors ranging from 1h to 3.3h depending on the lowest switching frequency that the buck regulator must operate at. to operate at 1mhz a 3.3h inductor should be used, while to operate at 3mhz a 1h inductor may be used. table 3 shows some recommended inductors for the buck regulators. the input supply needs to be decoupled with a 10f capacitor while the output needs to be decoupled with a 22f capacitor. refer to capacitor selection for details on selecting a proper capacitor. each buck regulator can be programmed via i 2 c. to program buck regulator 1 use sub-address 01h, buck regulator 2 sub-address 02h, buck regulator 3 sub-address 03h, buck regulator 4 sub address 04h, buck regulator 5 sub-address 05h, buck regulator 6 sub-address 06h, buck regulator 7 sub-address 07h, and buck regulator 8 sub-address 08h. the bit format is explained in table 7. combined buck regulators a single 2a buck regulator is available by combining two adjacent 1a buck regulators together. likewise a 3a or 4a buck regulator is available by combining any three or four adjacent buck regulators respectively. tables 4, 5, and 6 show recommended inductors for these configurations. the input supply needs to be decoupled with a 22f capaci - tor while the output needs to be decoupled with a 47f capacitor for a 2a combined buck regulator. likewise for 3a and 4a configurations the input and output capacitance must be scaled up to account for the increased load. refer to capacitor selection in the applications information sec - tion for details on selecting a proper capacitor. in many cases, any extra unused buck converters may be used to increase the efficiency of the active regulators. in general the efficiency will improve for any regulators running close to their rated load currents. if there are unused regulators, the user should look at their specific applications and current requirements to decide whether to add extra stages. table 3. recommended inductors for 1a buck regulators part number l (h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer ihlp1212aber1r0m-11 1.0 3 38 3 3.6 1.2 vishay 1239as-h-1r0n 1 2.5 65 2.5 2.0 1.2 toko xfl4020-222me 2.2 3.5 23.5 4 4 2.1 coilcraft 1277as-h-2r2n 2.2 2.6 84 3.2 2.5 1.2 toko ihlp1212bzer2r2m-11 2.2 3 46 3 3.6 1.2 vishay xfl4020-332me 3.3 2.8 38.3 4 4 2.1 coilcraft ihlp1212bzer3r3m-11 3.3 2.7 61 3 3.6 1.2 vishay ltc3375 3375fa
27 for more information www.linear.com/3375 a pplica t ions i n f or m a t ion table 7. global buck regulator program register bit format bit7 enable default is 0 which disables the part. a buck regulator can also be enabled via its enable pin. when enabled via pin, the contents of the i 2 c register program its functionality. bit6 mode default is 0 which is burst mode operation. a 1 programs the regulator to operate in forced continuous mode. bit5(phase1) bit4(phase0) phase control default varies per converter . 00 programs a sw high transition to coincide with the internal clock rising edge. 01 programs a 90 offset, 10 programs a 180 offset, and 11 programs a 270 offset. bit3(dac3) bit2(dac2) bit1(dac1) bit0(dac0) dac control these bits are used to program the feedback regulation voltage. default is 1100 which programs a voltage of 725mv . bits 0000 program the lowest feedback regulation of 425mv , and 1111 programs a full-scale voltage of 800mv. an lsb (dac0) has a bit weight of 25mv. table 4. recommended inductors for 2a buck regulators part number l (h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer xfl4020-102me 1.0 5.1 11.9 4 4 2.1 coilcraft 74437324010 1 9 27 4.45 4.06 1.8 wurth elektronik xal4020-222me 2.2 5.6 38.7 4 4 2.1 coilcraft fdv0530-2r2m 2.2 5.3 15.5 6.2 5.8 3 toko ihlp2020bzer2r2m-11 2.2 5 37.7 5.49 5.18 2 vishay xal4030-332me 3.3 5.5 28.6 4 4 3.1 coilcraft fdv0530-3r3m 3.3 4.1 34.1 6.2 5.8 3 toko table 5. recommended inductors for 3a buck regulators part number l (h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer xal4020-102me 1.0 8.7 14.6 4 4 2.1 coilcraft fdv0530-1r0m 1 8.4 11.2 6.2 5.8 3 toko xal5030-222me 2.2 9.2 14.5 5.28 5.48 3.1 coilcraft ihlp2525czer2r2m-01 2.2 8 20 6.86 6.47 3 vishay 74437346022 2.2 6.5 20 7.3 6.6 2.8 wurth elektonik xal5030-332me 3.3 8.7 23.3 5.28 5.48 3.1 coilcraft spm6530t-3r3m 3 7.3 27 7.1 6.5 3 tdk table 6. recommended inductors for 4a buck regulators part number l (h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer xal5030-122me 1.2 12.5 9.4 5.28 5.48 3.1 coilcraft spm6530t-1r0m120 1 14.1 7.81 7.1 6.5 3 tdk xal5030-222me 2.2 9.2 14.5 5.28 5.48 3.1 coilcraft spm6530t-2r2m 2.2 8.4 19 7.1 6.5 3 tdk ihlp2525ezer2r2m-01 2.2 13.6 20.9 6.86 6.47 5 vishay xal6030-332me 3.3 8 20.81 6.36 6.56 3.1 coilcraft fdve1040-3r3m 3.3 9.8 10.1 11.2 10 4 toko ltc3375 3375fa
28 for more information www.linear.com/3375 a pplica t ions i n f or m a t ion v cc shunt regulator if load steps seen on v cc are of great concern, then the compensation capacitor should be tied from v cc to ground as shown in figure 6a. if load steps are not of a concern, but instead smaller compensation components are desired then the compensation capacitor should be tied from v shnt to ground as shown in figure 6b. for an npn device the pullup resistor between v shnt and the supply voltage should be sized such that: r pullup < v supply(minimum) ? (v cc + v be ) i vcc(max) ? where v supply(minimum) is the lowest possible collector voltage, v be and are specific to the npn in the applica - tion, and i vcc(max) is the maximum desired load current from v cc . likewise r pullup may be sized such to current limit i vcc from an npn device to prevent damage to the circuit from a short on the v cc pin, and to prevent the npn from exceeding its safe operating current: r pullup > v supply(maximum) ? (v cc + v be ) i vcc(limit) ? where v cc = 0v in the case of a grounded output. alternatively, the current may be limited by adding a re - sistor between v cc and the emitter of the npn such that: r lim = 6.1v ? (v cc + v be ) i vcc(limit) in this case when i vcc exceeds i vcc(limit) v cc will start to collapse. the npn should be sized to be able to survive at least: i vcc(max) = 6.1v ? v be r lim for the given supply voltage, where 6.1v is the maximum v shnt voltage (typical). the user should verify that the circuit is stable over the specific conditions of the desired application. in general increasing the value of the compensation capacitor used or increasing r pullup can improve stability. the user should keep in mind that increasing r pullup also decreases i vcc(max) . in general the highest v supply at i vcc(max) yields the worst stability for the circuit in figure 6a, while the highest v supply at no load on v cc yields the worst stability for the circuit in figure 6b. + ? fbv cc 1.02m v cc v shnt 3375 f06a 1.2v v cc regulator 301k 1 22f 576k + ? fbv cc 1.02m v cc v shnt 3375 f06b 1.2v v cc regulator 301k 576k 2.2f figure 6a. v cc regulator compensated from the v cc pin figure 6b. v cc regulator compensated from the v shnt pin the exact components used in the v cc shunt regulator are dependent on the specific conditions used in the applica - tion. care should be taken to make sure that the power dissipation limits of the specific n-type device used are not exceeded, because damage to the external device can lead to damage to the l tc3375. ltc3375 3375fa
29 for more information www.linear.com/3375 a pplica t ions i n f or m a t ion in general the circuit in 6a is recommended if the appli - cation needs to drive any external circuitry with v cc or if the larger compensation capacitor is tolerable. if v cc is only needed to drive the ltc3375 and smaller component sizes are critical, then the circuit in figure 6b may be used. input and output decoupling capacitor selection the ltc3375 has individual input supply pins for each buck switching regulator. each of these pins must be decoupled with low esr capacitors to gnd. these capacitors must be placed as close to the pins as possible. ceramic dielectric capacitors are a good compromise between high dielectric constant and stability versus temperature and dc bias. note that the capacitance of a capacitor deteriorates at higher dc bias. it is important to consult manufacturer data sheets and obtain the true capacitance of a capacitor at the dc bias voltage it will be operated at. for this rea - son, avoid the use of y5v dielectric capacitors. the x5r/ x7r dielectric capacitors offer good overall per formance. the input supply voltage pins 2, 5, 8, 11, 26, 29, 32 and 35 all need to be decoupled with at least 10f capacitors. choosing the c t capacitor the c t capacitor may be used to program the timing parameters associated with the pushbutton. for a given c t capacitor the timing parameters may be calculated as below. c t is in units of f. t pb_lo = 5000 ? c t ms t pb_on = 20000 ? c t ms t pb_off = 1000 ? c t seconds t hr = 100 ? c t seconds t irq _pw = 5000 ? c t ms t killh = 1000 ? c t seconds t killl = 5000 ? c t ms t rst = 23000 ? c t ms programming the global register the global register contains functions that either act on the ltc3375 top level or act on all buck switching regula - tors at once. these functions are described in table 8. the default structure is 0000 0000b. programming the rst and irq mask registers the rst mask register can be programmed by the user at sub-address 09h and its format is shown in table 9. if a bit is set to 1, then the corresponding regulators pgood will pull rst low if a pgood fault were to occur. the default for this register is ffh. the irq mask registers have the same bit format as the rst mask register. the irq mask registers are located at sub-addresses 0ah and 0bh and their default contents are 00h. status byte read back when either the rst or irq pin is pulled low, it indicates to the user that a fault condition has occurred. to find out the exact nature of the fault, the user can read the status registers. there are three registers that contain status information. the register at sub-address 0ch provides pgood fault condition reporting, while the register at sub-address 0dh provides uvlo fault condition reporting. these bits are all latched at interrupt. if any of the bits are disabled via masking, then their real time, unlatched status information is still available. bit7 of the register at sub-address 0eh provides latched information on the status of the dt warning. figure?4 shows the operation of the status registers. the contents of the irq status register are cleared when a clrint signal is issued. a pgood bit is a 0 if the regulators output voltage is more than 7.5% below its programmed value. a uvlo bit is a 0 if the associated v in is above its input uvlo threshold. the format for the status registers is shown in table 10. a write operation cannot be performed to any of these status registers. ltc3375 3375fa
30 for more information www.linear.com/3375 table 8. global control program register bit format bit7 reset_all default is 0. when asserted all buck converters will power down for 1 second after which the bit will clear itself. bit6(dt1) bit5(dt0) dt warning control default is 00 which deactivates the dt warning. 01 programs C140, 10 programs C125, and 11 programs C110. bit4 ignore_en default is 0 which allows the en pins to power on the buck converters. when written to 1 the enable pins will be ignored. this allows power-down sequencing via i 2 c even if the en pins are tied to a logic high voltage source. bit3 1kpd default is 0 in which the sw node remains in a high impedance state when the regulator is in shutdown. a 0 pulls the sw node to gnd through a 10k resistor. this bit acts on all buck converters at once. bit2 slow edge this bit controls the slew rate of the switch node. default is 0 which enables the switch node to slew at a faster rate, than if the bit were programmed a 1. this bit acts on all buck converters at once. bit1 rd_temp default is 0. this bit commands the temperature a/d to sample the voltage present at the temp pin. after a read is complete this bit will clear itself. bit0 unused this bit is unused and must be written to 0 a pplica t ions i n f or m a t ion table 9 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pgood[8] pgood[7] pgood[6] pgood[5] pgood[4] pgood[3] pgood[2] pgood[1] table 10 sub- address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0ch pgood[8] pgood[7] pgood[6] pgood[5] pgood[4] pgood[3] pgood[2] pgood[1] 0dh uvlo[8] uvlo[7] uvlo[6] uvlo[5] uvlo[4] uvlo[3] uvlo[2] uvlo[1] 0eh dt_warn temp[6] temp[5] temp[4] temp[3] temp[2] temp[1] temp[0] pcb considerations when laying out the printed circuit board, the following list should be followed to ensure proper operation of the ltc3375: 1. the exposed pad of the package (pin 49) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. all the input supply pins should each have a decoupling capacitor. 3. the connections to the switching regulator input supply pins and their respective decoupling capacitors should be kept as short as possible. the gnd side of these capacitors should connect directly to the ground plane of the part. these capacitors provide the ac current to the internal power mosfets and their drivers. it is important to minimize inductance from these capacitors to the v in pins of the ltc3375. 4. the switching power traces connecting sw1, sw2, sw3, sw4, sw5, sw6, sw7 and sw8 to their respec - tive inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, high input impedance sensitive nodes, such as the feedback nodes, should be kept far away or shielded from the switching nodes or poor performance could result. 5. the gnd side of the switching regulator output capaci - tors should connect directly to the thermal ground plane of the part. minimize the trace length from the output capacitor to the inductor(s)/pin(s). 6. in a combined buck regulator application the trace length of switch nodes to the inductor must be kept equal to ensure proper operation. ltc3375 3375fa
31 for more information www.linear.com/3375 typical a pplica t ions ltc3375 exposed pad pb 2.2h 0.01f push button v in1 sw1 fb1 v in8 sw8 fb8 3375 f07 2.2h 649k 432k 1.02m 287k 10f 3.3v to 5.5v 1.8v 1a 3.3v 1a 22f 22f 10f 2.25v to 5.5v 2.2h v in2 sw2 fb2 v in7 sw7 fb7 2.2h 464k 432k 1.07m 340k 10f 3v to 5.5v 1.5v 1a 3v 1a 22f 22f 10f 2.25v to 5.5v 2.2h v in3 sw3 fb3 v in6 sw6 fb6 2.2h 422k 649k 1.02m 412k 10f 2.5v to 5.5v 1.2v 1a 2.5v 1a 22f 22f 10f 2.25v to 5.5v 2.2h v in4 sw4 fb4 sda scl v cc c t 402k rt wdi en1 en2 en3 en4 en5 en6 en7 en8 kill sync v in5 sw5 fb5 v shnt fbv cc irq rst wdo on temp v cc microprocessor control i 2 c control 2.2h 280k 732k 301k 1.02m 576k high voltage > 4.0v 732k 412k 10f 2.25v to 5.5v 1v 1a 2v 1a 22f 1f 22f microprocessor control 10f 2.25v to 5.5v 2.2f figure 7. detailed front page application circuit ltc3375 3375fa
32 for more information www.linear.com/3375 typical a pplica t ions figure 8. buck regulators with sequenced start-up driven from a high voltage upstream buck converter ltc3375 exposed pad pb 2.2h 0.01f push button v in1 sw1 fb1 v in8 sw8 fb8 3375 f08 2.2h 422k 649k 422k 649k 10f 1.2v 1a 2.5v 1a 1.8v 1a 1.6v 1a 1.2v 1a 10f 10f 10f 10f 10f 10f 10f 22f 22f 22f 22f 2.5v 1a 1.8v 1a 1.6v 1a 22f 22f 22f 22f 2.2h v in2 sw2 fb2 v in7 sw7 fb7 2.2h 1.02m 412k 1.02m 412k 2.2h v in3 sw3 fb3 v in6 sw6 fb6 2.2h 649k 432k 649k 432k 2.2h v in4 sw4 fb4 v cc sda scl c t 402k rt kill sync wdi en1 en2 en3 en4 en5 en6 en7 en8 v in5 sw5 fb5 v shnt v cc fbv cc irq rst wdo temp on microprocessor control i 2 c control 2.2h 511k 422k 47k 215 3.3v 5ma 1 22f 1.02m 576k 511k 422k 1f microprocessor control high voltage 5.5v to 60v fzt6928 0.1f c in 22f v in 5.5v to 60v intv cc 34.8k 470pf 100k 100k mtop, mbot: si7850dp l1 coilcraft ser1360-802kl c out : sanyo 10tpe330m d1: dfls1100 19.1k 2.2f d1 0.1f freq ith sgnd sgnd ltc3891 v in pgood pllin/mode i lim intv cc pgnd l1 8h r sense 7m boost sw bg sense + sense ? extv cc v fb tg mtop mbot 1nf c out 330f 5v 6a track/ss run ltc3375 3375fa
33 for more information www.linear.com/3375 typical a pplica t ions figure 9. combined buck regulators with common input supply ltc3375 exposed pad pb 2.2h 0.01f push button v in1 sw1 sw2 sw3 sw4 fb1 v in6 sw8 sw7 sw6 fb6 3375 f09 2.2h 422k 649k 1.02m 412k 1.2v 3a 2.5v 4a 2.7v to 5.5v 100f 68f 10f 10f 10f 10f 10f 10f 10f 10f 10f v in2 fb2 v in7 fb7 v in3 fb3 v in8 fb8 2.2h v in4 fb4 sda scl c t rt wdi en1 en5 en6 kill sync en2 en3 en4 en7 en8 v in5 sw5 fb5 v shnt fbv cc irq rst wdo on temp v cc microprocessor control i 2 c control 511k 422k 1.6v 1a 1f 22f microprocessor control ltc3375 3375fa
34 for more information www.linear.com/3375 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) ltc3375 3375fa
35 for more information www.linear.com/3375 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/13 clarified v cc input supply current specification clarified rst pin functionality clarified buck regulators with combined power stages clarified table 6 recommended inductor ratings 4 12 16, 17 27 ltc3375 3375fa
36 for more information www.linear.com/3375 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3675 7-channel configurable high power pmic four parallelable buck dc/dcs (1a, 1a, 500ma, 500ma), 1a boost, 1a buck-boost, 25ma ldo, dual string led driver, pushbutton, i 2 c control ltc3589/LTC3589-1 8-output regulator with sequencing and i 2 c three buck dc/dcs, three 250ma ldos, 25ma ldo, 1.2a buck-boost, pushbutton, i 2 c control ltc3375 exposed pad pb 1h 0.01f push button paper clip hole push button v in1 v in2 fb2 v in8 v in7 fb8 3375 ta02 1.02m 287k 10f 2.25v to 5.5v 3.3v to 5.5v 1.8v 3a 2.25v to 5.5v 1.2v 1a 3.3v 2a 2.5v to 5.5v 10f 10f 10f 10f 10f 47f 22f 68f v in3 fb3 10f 10f sw1 sw2 sw3 fb1 sw7 sw8 fb7 1h 649k 432k v in4 sw4 fb4 fb5 1h 422k 649k v cc scl sda c t 267k rt wdi en1 en4 en5 en7 en2 en3 en6 en8 v shnt v cc fbv cc irq rst wdo temp sync on kill i 2 c control 301k 1.02m 2.2f 576k 1f microprocessor control high voltage >4.0v v in6 v in5 fb6 1h 1.02m 412k 2.5v 2a 47f sw5 sw6 combined bucks with 3mhz switch frequency, sequenced power up, and kill based hardware override shut down linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/3375 linear technology corporation 2013 lt 0313 rev a ? printed in usa ltc3375 3375fa

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